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Ordering number : ENN 6903
Bi-CMOS IC
LV23000M
Single-Chip Tuner IC for Radio/Cassette Players
Overview
The LV23000M is a single-chip tuner IC for radio/cassette players that provides FM, AM, MPX, and PLL circuits. It allows the tuner PCB to be simplified significantly.
Package Dimensions
unit: mm 3129-MFP36SD
[LV23000M]
36 19
Functions
* AM tuner * FM tuner * Multiplex stereo decoder * PLL frequency synthesizer
Features
* Tuner circuit includes built-in PLL for easy end product design. * Supports FCC standards * Built-in adjustment-free multiplex VCO * AM low-cut control * Provides the transistor required to implement an active low-pass filter.
15.3 2.25 2.5max 0.65
1
18
0.25
0.4
0.8
0.85
SANYO: MFP36SD (375 mil)
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
62901RM (OT) No. 6903-1/14
0.1
9.2 10.5
7.9
LV23000M
Specifications
Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Symbol VCC max VDD max VIN1 max VIN2 max Pdmax VO1 max Maximum output voltage VO2 max VO3 max Operating temperature Storage temperature Topr Tstg VCC VDD CE, DI, CL XIN Ta 70C* DO XOUT, PD BO1, BO2, AOUT Conditions Ratings 7.0 7.0 7.0 VDD + 0.3 400 7.0 VDD + 0.3 12.0 -20 to +70 -40 to +125 Unit V V V V mW V V V C C
Maximum input voltage Allowable power dissipation
Note: * When mounted on a 114.3 x 76.1 x 1.6 mm glass epoxy printed circuit board.
Operating Conditions at Ta = 25C
Parameter Recommended supply voltage Symbol VCC VDD VCC op VDD op Conditions Ratings 5.0 3.0 4.0 to 6.0 2.5 to 3.6 Unit V V V V
Operating supply voltage range
PLL Block Allowable Operating Ranges at Ta = -20 to +70C, VSS = 0 V
Parameter Supply voltage High-level input voltage Low-level input voltage Output voltage Symbol VDD VIH VIL VO1 VO2 fIN1 Operating frequency fIN2 fIN3 fIN4 CE, CL, DI CE, CL, DI DO BO1, BO2, AOUT XIN: VIN1 FMIN: VIN2 AMIN (SNS = 1): VIN3 AMIN (SNS = 0): VIN4 10 2 0.5 Conditions Ratings min 2.5 0.7VDD 0 0 0 75 160 40 10 typ max 3.6 6.0 0.3VDD 6.0 10 Unit V V V V V kHz MHz MHz MHz
Note: The XIN pin has an extremely high input impedance, which may result in current leakage problems.
No. 6903-2/14
LV23000M Operating Characteristics at Ta = 25C, VCC = 5.0 V, VDD = 3.0 V, in the specified test circuit, using Yamaichi Electronics socket IC51-0362-736
Parameter Symbol Conditions Ratings min typ max Unit
[FM Front End Characteristics] : fc = 98 MHz, fm = 1 kHz, 22.5 kHzdev. 3 dB sensitivity Practical sensitivity 3 dB LS QS 60 dBV EMF, referenced to a 22.5 kHz dev. output, -3 dB input For a 30 dB signal-to-noise ratio input 12 12 dBV EMF dBV EMF
[FM IF Monaural Characteristics] : fc = 10.7 MHz, fm = 1 kHz, 75 kHzdev. Demodulator output Signal-to-noise ratio Total harmonic distortion (mono) 3 dB sensitivity IF counter sensitivity Muting attenuation VO S/N THD 3 dB LS IF-C3 Mute-Att 100 dB V, the pin 12 output 100 dB V, the pin 12 output 100 dB V, the pin 12 output 100 dB V, referenced to a 75 kHz dev. output, -3 dB input SDC0 = 1, SDC1 = 0, the pin 18 (DO) output 100 dB V, the pin 12 output 41 210 68 330 75 0.3 38 51 68 1.5 44 61 420 mVrms dB % dBV dBV dB
[FM IF Stereo Characteristics] : fc = 10.7 MHz, fm = 1 kHz, L+R = 90%, Pilot = 10% Separation Total harmonic distortion (main) SEP THD 100 dB V, L-mod, Pin 12 output/pin 13 output 100 dB V, main modulation, the pin 12 output 28 40 0.5 1.5 dB %
[AM Characteristics] : fc = 1000 kHz, fm = 1 kHz, 30% mod Detector output 1 Detector output 2 Signal-to-noise ratio 1 Signal-to-noise ratio 2 Total harmonic distortion IF counter sensitivity AM low cut [Current Drain] FM tuner block AM tuner block PLL block [PLL Characteristics] Built-in feedback resistor Built-in output resistor Hysteresis High-level output voltage Rf Rd VHIS VOH VOL1 VOL2 Low-level output voltage VOL2 VOL3 VOL4 IIH1 High-level input current IIH2 IIH3 IIL1 Low-level input current IIL2 IIL3 Output leakage current High-level 3-state off leakage current Low-level 3-state off leakage current IOFF1 IOFF2 IOFFH IOFFL XIN XOUT CE, CL, DI PD: IO = -1 mA PD: IO = 1 mA BO1, BO2: IO = 1 mA BO1, BO2: IO = 5 mA DO: IO = 1 mA AOUT: IO = 1 mA, AIN = 2.0 V CE, CL, DI: VI = 6.0 V XIN: VI = VDD AIN: VI = 6.0 V CE, CL, DI: VI = 0 V XIN: VI = 0 V AIN: VI = 0 V AOUT, BO1, BO2: VO = 10 V DO: VO = 6.0 V PD: VO = 6.0 V PD: VO = 0 V 0.01 0.01 0.16 0.16 VDD - 1.0 1.0 0.25 1.25 0.25 0.5 5.0 0.9 200 5.0 0.9 200 5.0 5.0 200 200 8 250 0.1VDD M k V V V V V V V A A nA A A nA A A nA nA ICCFM ICCAM IDD In FM mode with no input In AM mode with no input fr = 83 MHz, X'tal = 75 kHz, With no input to the tuner block 20 10 1 30 20 2 40 30 5 mA mA mA VO1 VO2 S/N1 S/N2 THD IF-C LOW-CUT 23 dB V, the pin 12 output 80 dB V, the pin 12 output 23 dB V, the pin 12 output 80 dB V, the pin 12 output 80 dB V, the pin 12 output The pin 18 (DO) output 80 dB V, referenced to fm = 1 kHz, the pin 12 output when fm = 100 Hz. 16 5 20 60 1.5 47 40 110 20 54 1.2 26 8 3.0 36 11 80 160 mVrms mVrms dB dB % dBV dB
No. 6903-3/14
(2) IN2 mode
DI
(1) IN1 mode
DI Address
Address
10010100
00010100
(9)O-PORT (4)IFSW (9)O-PORT (5)BDSW (14)STSW (15)SDC0 (6)DO-C
Structure of the DI Control Data (Serial Input Data)
(1)P-CTR
LV23000M
(7)UNLOCK (8)DZ-C (3)IF-CTR (16)SDC1 (10)PD-C (11)IFS (12)TEST
(3)IF-CTR (13)Don't care
0 1 0 BO1 IFSW B02 BDSW1 STSW SDC0 DOC0 DOC1 DOC2 UL0 UL1 DZ0 DZ1 GT0 GT1 SDC1 DLC IFS TEST0 TEST1 TEST2 (23)R-CTR P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 SNS DVS CTE DNC R0 R1 R2 R3
No. 6903-4/14
LV23000M Description of the DI Control Data
No. Control block/data Description * Specifies the divisor used by the programmable dividers. This is a binary value with P15 as the MSB. The LSB depends on DVS and SNS. DVS 1 Programmable divider data (1) P0 to P15 DVS, SNS 0 0 SNS * 1 0 LSB P0 P0 P4 Divisor setting (N) 272 to 65535 272 to 65535 4 to 4095 Actual divisor The actual setting times 2 The actual setting The actual setting Related data
Note: When P4 is the LSB, bits P0 to P3 are ignored. * Selects the input signal (FMIN or AMIN) to the programmable divider and switches the input frequency range. (* : don't care) DVS 1 0 0 SNS * 1 0 Input FMIN AMIN AMIN Operating frequency range 10 to 160 MHz 2 to 40 MHz 0.5 to 10 MHz
* Data that selects the reference frequency (fref) R3 0 0 0 0 0 0 0 Reference divider data (2) R0 to R3 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference frequency 25 kHz 25 kHz 25 kHz 25 kHz 12.5 kHz 6.25 kHz 3.125 kHz 3.125 kHz 5 kHz 5 kHz 5 kHz 1 kHz 3 kHz 15 kHz PLL INHIBIT + X'tal OSC STOP PLL INHIBIT
Note: PLL INHIBIT * In this state, the programmable divider block and the IF counter block are stopped, FMIN, AMIN, and IFIN are pulled down (to ground), and the charge pump goes to the highimpedance state.
* Measurement start data for the IF counter CTE = 1: Start the count. = 0: Reset the counter. IF counter control data (3) * Determines the measurement time for the general-purpose counter. GT0 CTE GT0, GT1 0 0 1 1 GT1 0 1 0 1 Measurement time 4 ms 8 ms 16 ms 32 ms Wait time 3 to 4 ms 3 to 4 ms 3 to 4 ms 3 to 4 ms IFS
Continued on next page.
No. 6903-5/14
LV23000M
Continued from preceding page.
No. Control block/data Mute control data (4) IFSW FM/AM band switching control data (5) BDSW * Determines the output of the DO pin. DOC2 0 0 0 0 1 1 1 1 DOC1 0 0 1 1 0 0 1 1 DOC0 0 1 0 1 0 1 0 1 DO pin state Open Low when the unlocked state is detected end-UC (See the section indicated with the asterisk (*) below.) Open Open Open Low when stereo detected Open Description * Determines the output of the IFSW output port and controls the muting function. Data = 0: Receive mode = 1: Muted * Determines the output of the BDSW output port and switches the reception band. Data = 0: AM = 1: FM Related data
* The open state is selected after the power on reset. DO pin control data (6) Note: end-UC: The IF counter measurement complete check. UL0, UL1 DOC0 DOC1 DOC2 CTE DO pin Count start Count end CE : HI
(1) If the end-UC setting is used, the DO pin will automatically go to the open state when an IF count operation starts (CTE transitions from 0 to 1). (2) When the IF counter measurement completes, the DO pin goes low and it becomes possible to check for the count completed state. (3) The DO pin goes to the open state when serial data I/O is performed (when the CE pin is high). Note: The DO pin goes to the open state during the data input period (IN1 and IN2 modes when CE is high), regardless of the values of the DO pin control data (DOC0:2). During the data output period (OUT mode when CE is high), the DO pin outputs the content of the internal DO serial data in synchronization with the CL signal, regardless of the values of the DO pin control data (DOC0:2).
Unlock detection data (7) UL0, UL1
* Phase error (oE) detection width selection data used for PLL lock state discrimination. The unlocked state is recognized when a phase error in excess of the specified detection width occurs. UL1 0 0 1 UL0 0 1 * oE detection width Stopped 0 6.67 Detection output Open Directly outputs oE Extends oE by 1 to 2 ms DOC0 DOC1 DOC2
Note: When the unlocked state is detected, the DO pin goes low and UL in the serial data output will be 0.
Continued on next page.
No. 6903-6/14
LV23000M
Continued from preceding page.
No. Control block/data * Controls the phase comparator dead band. DZ1 Phase comparator control data (8) DZ0, DZ1 0 0 1 1 DZ0 0 1 0 1 Dead band mode DZA DZB DZC DZD Description Related data
Dead band widths: DZA < DZB < DZC < DZD Output port data (9) BO1, BO2 * Sets the outputs from the BO1 and BO2 output ports. Data = 0: Open = 1: Low * Forcibly controls the state of the charge pump output. DLC Charge pump control data (10) DLC If deadlock occurs due to VCO oscillation when the VCO control voltage (Vtune) is 0 V, the deadlock can be released by setting the charge pump output low and setting Vtune to VCC. (This is referred to as a deadlock clear circuit.) * This bit should normally be set to 1. However, setting this bit to 0 sets the device to degraded input sensitivity mode, and the input sensitivity is reduced by about 10 to 30 mV rms. * IC test data IC test data (12) TEST0 toTEST2 TEST0 TEST1 TEST2 All these bits are set to 0 after the power on reset. (13) DNC Forced mono control data (14) STSW * This bit must be set to 0. All bits must be set to 0. 0 1 Charge pump output Normal operation Forced to the low level.
(11)
IFS
* Determines the output of the STSW output port and controls the forced stereo function. Data = 0: Mono = 1: Stereo
* Determines the outputs of the SDC0 and SDC1 ports and sets the SD sensitivity. SD sensitivity adjustment data SDC0 0 SDC0 SDC1 0 1 1 SDC1 0 1 0 1 SD sensitivity (typ) 42 dBV 45 dBV 51 dBV 56 dBV
(15) (16)
No. 6903-7/14
LV23000M Structure of the DO Control Data (Serial Output Data) (1) OUT mode
Address DI 01010100
DO
(1)IN-PORT
DO Output Data
No. Control block/data Stereo indicator SD indicator (1) Control data Description Related data
* Indicates the states of the stereo and SD indicators at the point latched. The data is latched at the point the devices goes to data output mode (OUT mode). STIND Stereo indicator state: 0: ST on, 1: ST off SDINC SD indicator state: 0: SD on, 1: SD off
STIND, SDIND
PLL unlocked data (2) UL
* Indicates the state of the unlock detection circuit at the point latched. UL 0: Unlocked 1: Locked or detection stopped mode.
(3)IF-CTR
STIND SDIND 0 UL C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
UL0 UL1
IF counter (3) Binary counter
* Indicates the content of the IF counter (20-bit binary counter) at the point latched. C19 MSB of the binary counter C0 LSB of the binary counter
CTE GT0 GT1
C19 to C0
No. 6903-8/14
LV23000M Serial Data Input (IN1 / IN2) tSU, tHD, tEL, tES, tEH 0.75s, tLC < 0.75s (1) CL: Normally high
tEL CE tES tEH
CL tSU DI Internal data B0 tHD B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC
(2) CL: Normally low
tEL CE tES tEH
CL tSU DI Internal data B0 tHD B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC
Serial Data Output (OUT) tSU, tHD, tEL, tES, tEH 0.75s, tDC, tDH < 0.35s (1) CL: Normally high
tEL CE tES tEH
CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 tDC DO I2 tDC I1 UL C3 C2 C1 tDH C0
(2) CL: Normally low
tEL CE tES tEH
CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 tDC DO I2 tDC I1 UL C3 C2 C1 tDH C0
Note: Since the DO pin is an n-channel open-drain output, the data transition times (tDC and tDH) depend on the value of the pull-up resistor and the printed circuit board capacitance.
No. 6903-9/14
LV23000M Serial Data Timing
CE tCH CL VIH DI VIL DO tLC Internal data latch Old New tSU tHD VIL tDC tDC tDH VIH VIL VIH tCL VIL tEL VIH tES VIL VIH tEH VIH
VIL
<>
CE tCH CL VIH VIL VIH DI VIL DO tLC Internal data latch Old New tSU tHD VIL tDC tDH VIH tCL VIH tEL VIL tES VIH tEH VIH
VIL
<>
Parameter Data setup time Data hold time Clock low-level time Clock high-level time CE wait time CE setup time CE hold time Data latch transition time Data output time
Symbol tSU tHD tCL tCH tEL tES tEH tLC tDC tDH
Pins DI, CL DI, CL CL CL CE, CL CE, CL CE, CL
Conditions
Ratings min 0.75 0.75 0.75 0.75 0.75 0.75 0.75 0.75 typ max
Unit s s s s s s s s s
DO, CL DO, CE
These times depend on the value of the pull-up resistors and the printed circuit board capacitances.
0.35
No. 6903-10/14
+B
LV23000M Block Diagram
VD D AM Low - cut
B.P.F
36
LPF FM OSC AM OSC
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GND2
VCC2
VDD
POWER ON RESET REFERENCE DEVIDER
FM RF SD FF VCO OSC BUFFER AGC FM S- METER FF FF PILOT DET PHASE COMP MUTE ST TRIG ST SW
PHASE DETECTOR CHARGE PUMP
LV23000M
PROGRAMMABLE DIVIDER
SWALLOW COUNTER
UNLOCK DETECTOR
AM RF
AM MIX
AM DET
FM DET
DATA SHIFT REGISTOR LATCH
FM MIX VCC 1 AM IF IF BUFFER FM IF DECODER VSS
UNIVERSAL COUNTER CCB I/F
REG
GND 1
1
2
3
4
5
6
7
8
9
10
11
12
L- OUT
13
R- OUT
14
15
16
17
18
AM ANT
MICROCONTROLLER
450kHz 10.7MHz
Vcc
No. 6903-11/14
Vt=8V 0.01 33k 33k 10 SVC383 16p 100k 0.33 51k 0.1 SW5 SW4 10k SW10 SW9 SW8 SW7 SW6 4.7k 22 + 0.01 330p 10k 100k 4.7 10p 10p CFV-206 100 + + 1000p 390p 0.047 1k 1k 5.1k V DD =3.0V 0.01
0.047 0.047
33k
1000p
10
10p
FM OSC
FM IN SA-181 51k
LV23000M Test Circuit Diagram
GFWB3 B.P.F
SVC201
FM RF
36
FM OSC BO2 BO1 A-OUT A-IN PD AM OSC AM AGC LOW CUT DET OUT MPX IN VDD
35
34
33
SVC201 8p
32
31
30
29
28
27
26
25
24
23
22
21
20
X-OUT
19
X-IN
FM RF IN
GND2
FM RF OUT
Vcc2
LV23000M
AM RF IN Vcc1 P-DET P-COMP
REG
FM MIX
GND1
AM MIX
AM IF IN
FM IF IN
FM DET
L-OUT
R-OUT
VSS
CE
DI
CL
DO
VDD
1
SW1 1 + + 4.7 3.3k 1 +
2
3
4
5
6
7
8
9
10
11
12
L-OUT 0.01
13
14
R-OUT 0.01
15
16
17
18
SW2 SW3 51k
0.047
AM ANT
51 SFU450B
39m
0.047 300 FM IF IN 51
+ 100
SFE10.7 MA5
0.047
10
CDA10.7 MG1
+
SA-164
MICROCONTROLLER
Vcc=5.0V 0.047
No. 6903-12/14
LV23000M
0 --10
FM characteristics
S-meter voltage, VSM -- V, Total harmonic distortion, THD -- %
75kHz 22.5kHz VCC=5V VDD=3V fc=83MHz fm=1kHz
FM characteristics
--20
Output -- dBm
VSM
--30 --40 --50 --60 --70 --80
VCC=5V VDD=3V fc=83MHz fm=1kHz 22.5kHzdev AM=30%mod
THD(75kHz) THD(22.5kHz)
Input -- dBV EMF
0 --10 --20
Input -- dBV EMF
AM characteristics
VAGC -- V, Total harmonic distortion,THD -- %
VCC=5V VDD=3V fc=1000kHz fm=1kHz 30%mod VCC=5V VDD=3V fc=1000kHz fm=1kHz
AM characteristics
Output -- dBm
--30 --40 --50 --60 --70 --80 --90
Input -- dBV
Input -- dBV
No. 6903-13/14
LV23000M
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of June, 2001. Specifications and information herein are subject to change without notice. PS No. 6903-14/14

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